Question:
I would like to know what voltage range my Pentium®
processor requires. How do I determine this?
Answer:
If your processor does not have the voltage markings
directly on the package (see above), use the s-spec number to determine this. The s-spec
is a 3-digit number on the processor package which follows SX, SK, SU, SY, or SZ.
Use the s-specs shown in the following table to find the
voltage requirements for your part.
Type |
Family |
Model |
Stepping |
Mfg.
Stepping |
Core/bus
[MHz] |
S-Spec |
Comments |
Notes |
0 |
5 |
2 |
1 |
B1 |
90/60 |
SX879 |
STD |
0 |
5 |
2 |
1 |
B1 |
90/60 |
SX885 |
MD |
0 |
5 |
2 |
1 |
B1 |
90/60 |
SX909 |
VR |
2 |
5 |
2 |
1 |
B1 |
90/60 |
SX874 |
DP, STD |
0 |
5 |
2 |
1 |
B1 |
100/66 |
SX886 |
MD |
0 |
5 |
2 |
2 |
B1 |
100/66 |
SX910 |
VR, MD |
0 |
5 |
2 |
2 |
B3 |
75/50 |
SX951 |
TCP Mobile |
0 |
5 |
2 |
2 |
B3 |
90/60 |
SX923 |
STD |
0 |
5 |
2 |
2 |
B3 |
90/60 |
SX922 |
VR |
0 |
5 |
2 |
2 |
B3 |
90/60 |
SX921 |
MD |
2 |
5 |
2 |
2 |
B3 |
90/60 |
SX942 |
DP, STD |
2 |
5 |
2 |
2 |
B3 |
90/60 |
SX943 |
DP, VR |
2 |
5 |
2 |
2 |
B3 |
90/60 |
SX944 |
DP, MD |
0 |
5 |
2 |
2 |
B3 |
90/60 |
SZ951 |
STD |
5 |
Type |
Family |
Model |
Stepping |
Mfg.
Stepping |
Core/bus
[MHz] |
S-Spec |
Comments |
Notes |
0 |
5 |
2 |
2 |
B3 |
100/66 |
SX960 |
VRE/ MD |
0 |
5 |
2 |
4 |
B5 |
75/50 |
SX975 |
TCP Mobile |
0 or 2 |
5 |
2 |
4 |
B5 |
75/50 |
SX961 |
STD |
0 or 2 |
5 |
2 |
4 |
B5 |
75/50 |
SZ977 |
STD |
5 |
0 or 2 |
5 |
2 |
4 |
B5 |
90/60 |
SX957 |
STD |
0 or 2 |
5 |
2 |
4 |
B5 |
90/60 |
SX958 |
VR |
0 or 2 |
5 |
2 |
4 |
B5 |
90/60 |
SX959 |
MD |
0 or 2 |
5 |
2 |
4 |
B5 |
90/60 |
SZ978 |
STD |
5 |
0 or 2 |
5 |
2 |
4 |
B5 |
100/66 |
SX962 |
VRE/MD |
0 |
5 |
2 |
5 |
C2 |
75/50 |
SK079 |
TCP Mobile |
0 or 2 |
5 |
2 |
5 |
C2 |
75/50 |
SX969 |
STD |
0 or 2 |
5 |
2 |
5 |
C2 |
75/50 |
SX998 |
MD |
Type |
Family |
Model |
Stepping |
Mfg.
Stepping |
Core/Bus
[MHz] |
S-Spec |
Comments |
Notes |
0 or 2 |
5 |
2 |
5 |
C2 |
75/50 |
SZ994 |
STD |
5 |
0 or 2 |
5 |
2 |
5 |
C2 |
75/50 |
SU070 |
STD |
6 |
0 or 2 |
5 |
2 |
5 |
C2 |
90/60 |
SX968 |
STD |
0 or 2 |
5 |
2 |
5 |
C2 |
90/60 |
SZ995 |
STD |
5 |
0 or 2 |
5 |
2 |
5 |
C2 |
90/60 |
SU031 |
STD |
6 |
0 or 2 |
5 |
2 |
5 |
C2 |
100/50 or 66 |
SX970 |
VRE/MD |
0 or 2 |
5 |
2 |
5 |
C2 |
100/50 or 66 |
SX963 |
STD |
0 or 2 |
5 |
2 |
5 |
C2 |
100/50 or 66 |
SZ996 |
STD |
5 |
0 or 2 |
5 |
2 |
5 |
C2 |
100/50 or 66 |
SU032 |
STD |
6 |
0 |
5 |
2 |
5 |
C2 |
120/60 |
SK086 |
VRE/MD |
0 |
5 |
2 |
5 |
C2 |
120/60 |
SX994 |
VRE/MD |
0 |
5 |
2 |
5 |
C2 |
120/60 |
SU033 |
VRE/MD |
6 |
0 |
5 |
2 |
5 |
C2 |
133/66 |
SK098 |
MD |
Type |
Family |
Model |
Stepping |
Mfg.
Stepping |
Core/Bus
[MHz] |
S-Spec |
Comments |
Notes |
0 |
5 |
2 |
5 |
mA1 |
75/50 |
SK089 |
VRT, TCP |
2,4 |
0 |
5 |
2 |
5 |
mA1 |
75/50 |
SK091 |
VRT, SPGA |
2,4 |
0 |
5 |
2 |
5 |
mA1 |
90/60 |
SK090 |
VRT,TCP |
2,4 |
0 |
5 |
2 |
5 |
mA1 |
90/60 |
SK092 |
VRT,SPGA |
2,4 |
0 or 2 |
5 |
2 |
B |
cB1 |
120/60 |
SK110 |
STD/no Kit |
3,4 |
0 or 2 |
5 |
2 |
B |
cB1 |
133/66 |
SK106 |
STD/no Kit |
3,4 |
0 or 2 |
5 |
2 |
B |
cB1 |
133/66 |
SK106J |
STD/no Kit |
3,4,7 |
0 or 2 |
5 |
2 |
B |
cB1 |
133/66 |
SK107 |
STD |
4 |
0 or 2 |
5 |
2 |
B |
cB1 |
133/66 |
SU038 |
STD/no Kit |
3,4,6 |
0 |
5 |
2 |
B |
mcB1 |
100/66 |
SY029 |
VRT, TCP |
2,4 |
0 |
5 |
2 |
B |
mcB1 |
120/66 |
SK113 |
VRT, TCP |
2,4 |
0 |
5 |
2 |
B |
mcB1 |
120/66 |
SK118 |
VRT, TCP |
2,4,7 |
0 |
5 |
2 |
B |
mcB1 |
120/66 |
SX999 |
3.3V, SPGA |
4 |
0 or 2 |
5 |
2 |
C |
cC0 |
150/60 |
SY015 |
STD |
0 or 2 |
5 |
2 |
C |
cC0 |
150/60 |
SU071 |
STD |
6 |
0 or 2 |
5 |
2 |
C |
cC0 |
166/66 |
SY016 |
STD |
3 |
0 or 2 |
5 |
2 |
C |
cC0 |
166/66 |
SY017 |
VRE |
0 or 2 |
5 |
2 |
C |
cC0 |
166/66 |
SU072 |
VRE/no kit |
3,6 |
0 |
5 |
2 |
C |
cC0 |
166/66 |
SY037 |
VRE,PPGA |
8,9 |
0 |
5 |
7 |
0 |
mA4 |
75/50 |
SK119 |
VRT, TCP |
2,4 |
Type |
Family |
Model |
Stepping |
Mfg.
Stepping |
Core/Bus
[MHz] |
S-Spec |
Comments |
Notes |
0 |
5 |
7 |
0 |
mA4 |
75/50 |
SK122 |
VRT, SPGA |
2,4 |
0 |
5 |
7 |
0 |
mA4 |
90/60 |
SK120 |
VRT, TCP |
2,4 |
0 |
5 |
7 |
0 |
mA4 |
90/60 |
SK123 |
VRT, SPGA |
2,4 |
0 |
5 |
7 |
0 |
mA4 |
100/66 |
SK121 |
VRT, TCP |
2,4 |
0 |
5 |
7 |
0 |
mA4 |
90/60 |
SK124 |
VRT, SPGA |
2,4 |
0 |
5 |
2 |
C |
mcC0 |
120/60 |
SY021 |
TCP,VRT |
2 |
0 |
5 |
2 |
C |
mcC0 |
120/60 |
SY027 |
SPGA 3.1V |
2 |
0 |
5 |
2 |
C |
mcC0 |
120/60 |
SY030 |
SPGA 3.3V |
2 |
0 |
5 |
2 |
C |
mcC0 |
133/66 |
SY019 |
TCP,VRT |
2 |
0 |
5 |
2 |
C |
mcC0 |
133/66 |
SY028 |
SPGA 3.1V |
2 |
0 |
5 |
2 |
6 |
E0 |
75/500 |
SY009 |
TCP,Mobile |
0 or 2 |
5 |
2 |
6 |
E0 |
75/50 |
SY005 |
STD |
0 or 2 |
5 |
2 |
6 |
E0 |
90/60 |
SY006 |
STD |
0 or 2 |
5 |
2 |
6 |
E0 |
100/66 |
SY007 |
STD |
0 or 2 |
5 |
2 |
6 |
E0 |
120/60 |
SY033 |
STD |
NOTES:
For a definition of STD, VR, VRE, MD, VRE/MD, refer to
Specification Changes 2 and 18 in this document. ES refers to Engineering Samples. DP
indicates that this part can only be used as a dual processor. CPU Type of
"2" or "0 or 2" indicates this part supports dual
processing.
The Type corresponds to bits [13:12] of the EDX register after RESET, bits [13:12] of the
EAX register after the CPUID instruction is executed. This is shown as 2 different values
based on the operation of the device as the primary processor or the dual processor
upgrade.
The Family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the
EAX register after the CPUID instruction is executed.
The Model corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX
register after the CPUID instruction is executed.
The Stepping corresponds to bits [3:0] of the EDX register after RESET, bits [3:0] of the
EAX register after the CPUID instruction is executed.
- TCASE = 60C.
- VRT Intel's Voltage Reduction Technology: The VCC for
I/O is 3.3V, but the core VCC, accounting for about 90% of power usage, is reduced
to 2.9V, to reduce power consumption and heating.
- No Kit means that part meets the specifications
but is not tested to support 82498/82493 and 82497/82492 cache timings
- STEPPING The cB1 stepping is logically equivalent to the
C2-step, but on a different manufacturing process. The mcB1 step is logically
equivalent to the cB1 step (except it does not support DP, APIC or FRC).
The mcB1, mA1, mA4 and mcC0-steps also use Intel's VRT (Voltage Reduction Technology, see
note 2 above) and are available in the TCP and SPGA package, primarily to support mobile
applications. All mobile steppings are distinguished by an additional "m"
prefix, for "mobile".
- This is a boxed Pentium processor without the attached fan
heatsink.
- This is a boxed Pentium processor with an attached fan
heatsink.
- These parts do not support boundary scan. S106J was
previously marked (and is the same as) SK106J.
- DP, FRC and APIC features are not supported on these parts.
- These parts are packaged in the Plastic Pin Grid Array
(PPGA) package. For additional specifications of this package, see specification
clarifications 27 and 28.
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